%0 Conference Paper %1 conf/vlsic/ZhangLLSKZ19 %A Zhang, Jie-Fang %A Lee, Ching-En %A Liu, Chester %A Shao, Yakun Sophia %A Keckler, Stephen W. %A Zhang, Zhengya %B VLSI Circuits %D 2019 %I IEEE %K dblp %P 306- %T SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#ZhangLLSKZ19 %@ 978-4-86348-720-8

@inproceedings{conf/vlsic/ZhangLLSKZ19, added-at = {2022-12-07T00:00:00.000+0100}, author = {Zhang, Jie-Fang and Lee, Ching-En and Liu, Chester and Shao, Yakun Sophia and Keckler, Stephen W. and Zhang, Zhengya}, biburl = {https://www.bibsonomy.org/bibtex/21e82bdbf4cb99c1e5f1fd4766415ede1/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2019}, ee = {https://doi.org/10.23919/VLSIC.2019.8778193}, interhash = {4b1fd2bfeda34544a8c1a03f0e73be71}, intrahash = {1e82bdbf4cb99c1e5f1fd4766415ede1}, isbn = {978-4-86348-720-8}, keywords = {dblp}, pages = {306-}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:13.000+0200}, title = {SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#ZhangLLSKZ19}, year = 2019 }