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Disambiguation of "Liu, Chester"

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SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS.

, , , , , and . VLSI Circuits, page 306-. IEEE, (2019)

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Alexander Chester

Andrew Chester

Chester Avilés

Liu Liu

Liu Liu

 

Other publications of authors with the same name

A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer., , and . CICC, page 1-2. IEEE, (2021)PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA., , , and . VLSI Circuits, page 1-2. IEEE, (2021)Implementation of a highly scalable blokus duo solver on FPGA.. FPT, page 482-485. IEEE, (2013)Placement Optimization of Flexible TFT Digital Circuits., , , , , and . IEEE Des. Test Comput., 28 (6): 24-31 (2011)A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS., , and . A-SSCC, page 233-236. IEEE, (2017)A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS., , and . IEEE J. Solid State Circuits, 53 (10): 2818-2827 (2018)NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging., , , , , , , , and . VLSI Technology and Circuits, page 208-209. IEEE, (2022)Static timing analysis for flexible TFT circuits., , , and . DAC, page 799-802. ACM, (2010)A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification., , , and . IEEE J. Solid State Circuits, 54 (7): 2081-2090 (2019)A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS., , and . VLSI Circuits, page 1-2. IEEE, (2016)