%0 Journal Article %1 journals/jssc/WangZLLWHCLYH24 %A Wang, Junjie %A Zhang, Teng %A Liu, Shuang %A Liu, Yihe %A Wu, Yuancong %A Hu, Shaogang %A Chen, Tupei %A Liu, Yang %A Yang, Yuchao %A Huang, Ru %D 2024 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 595-604 %T Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip. %U http://dblp.uni-trier.de/db/journals/jssc/jssc59.html#WangZLLWHCLYH24 %V 59

@article{journals/jssc/WangZLLWHCLYH24, added-at = {2024-04-01T00:00:00.000+0200}, author = {Wang, Junjie and Zhang, Teng and Liu, Shuang and Liu, Yihe and Wu, Yuancong and Hu, Shaogang and Chen, Tupei and Liu, Yang and Yang, Yuchao and Huang, Ru}, biburl = {https://www.bibsonomy.org/bibtex/2438b0c364bed60031d2fa3c72c186fb7/dblp}, ee = {https://doi.org/10.1109/JSSC.2023.3304174}, interhash = {aa350debe1432eb7ea3f2d4dceaf248f}, intrahash = {438b0c364bed60031d2fa3c72c186fb7}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, month = {February}, number = 2, pages = {595-604}, timestamp = {2024-04-08T10:42:17.000+0200}, title = {Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc59.html#WangZLLWHCLYH24}, volume = 59, year = 2024 }