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Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.

J. Wang, T. Zhang, S. Liu, Y. Liu, Y. Wu, S. Hu, T. Chen, Y. Liu, Y. Yang, and R. Huang. IEEE J. Solid State Circuits, 59 (2): 595-604 (February 2024)

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Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

Other publications of authors with the same name

Quantized STDP-based online-learning spiking neural network.S. Hu, G. Qiao, T. Chen, Q. Yu, Y. Liu, and L. Rong. Neural Comput. Appl., 33 (19): 12317-12332 (2021)An energy-efficient deep convolutional neural networks coprocessor for multi-object detection.Y. Wu, J. Wang, K. Qian, Y. Liu, R. Guo, S. Hu, Q. Yu, T. Chen, Y. Liu, and L. Rong. Microelectron. J., (2020)Application of Deep Compression Technique in Spiking Neural Network Chip.Y. Liu, K. Qian, S. Hu, K. An, S. Xu, X. Zhan, J. Wang, R. Guo, Y. Wu, T. Chen and 2 other author(s). IEEE Trans. Biomed. Circuits Syst., 14 (2): 274-282 (2020)STBNN: Hardware-friendly spatio-temporal binary neural network with high pattern recognition accuracy.G. Qiao, S. Hu, T. Chen, L. Rong, N. Ning, Q. Yu, and Y. Liu. Neurocomputing, (2020)Mechanism of nitrogen-enhanced negative bias temperature instability in pMOSFET.S. Tan, T. Chen, C. Ang, and L. Chan. Microelectron. Reliab., 45 (1): 19-30 (2005)Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network.D. Kong, S. Hu, Y. Wu, J. Wang, C. Xiong, Q. Yu, Z. Shi, Z. Liu, T. Chen, Y. Yin and 2 other author(s). IEEE Access, (2018)Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.J. Wang, T. Zhang, S. Liu, Y. Liu, Y. Wu, S. Hu, T. Chen, Y. Liu, Y. Yang, and R. Huang. IEEE J. Solid State Circuits, 59 (2): 595-604 (February 2024)Design of AM Self-Capacitive Transparent Touch Panel Based on a-IGZO Thin-Film Transistors.K. Wu, J. Zhang, Y. Li, X. Wang, Y. Liu, Q. Yu, and T. Chen. IEEE Access, (2020)Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range.R. Guo, K. Qian, J. Wei, T. Chen, Y. Liu, D. Kong, J. Wang, Y. Wu, S. Hu, Q. Yu and 1 other author(s). IEEE Access, (2019)3D Geometric Engineering of the Double Wedge-Like Electrodes for Filament-Type RRAM Device Performance Improvement.J. Sun, Y. Li, Y. Ye, J. Zhang, G. Chong, J. Tan, Z. Liu, and T. Chen. IEEE Access, (2020)

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Disambiguation of "Chen, Tupei"

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Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.

Please choose a person to relate this publication to

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Tupei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.

Please choose a person to relate this publication to

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.