%0 Journal Article %1 journals/jssc/KarlWNGHMKBZMB13 %A Karl, Eric %A Wang, Yih %A Ng, Yong-Gee %A Guo, Zheng %A Hamzaoglu, Fatih %A Meterelliyoz, Mesut %A Keane, John %A Bhattacharya, Uddalak %A Zhang, Kevin %A Mistry, Kaizad %A Bohr, Mark %D 2013 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 150-158 %T A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. %U http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#KarlWNGHMKBZMB13 %V 48

@article{journals/jssc/KarlWNGHMKBZMB13, added-at = {2021-10-14T00:00:00.000+0200}, author = {Karl, Eric and Wang, Yih and Ng, Yong-Gee and Guo, Zheng and Hamzaoglu, Fatih and Meterelliyoz, Mesut and Keane, John and Bhattacharya, Uddalak and Zhang, Kevin and Mistry, Kaizad and Bohr, Mark}, biburl = {https://www.bibsonomy.org/bibtex/2e0aafafa0bb79efca8e6e560d341111f/dblp}, ee = {https://doi.org/10.1109/JSSC.2012.2213513}, interhash = {b030a11d0c6b582ae9f15e1e16902e90}, intrahash = {e0aafafa0bb79efca8e6e560d341111f}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {150-158}, timestamp = {2024-04-08T10:42:17.000+0200}, title = {A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#KarlWNGHMKBZMB13}, volume = 48, year = 2013 }