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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.

E. Karl, Y. Wang, Y. Ng, Z. Guo, F. Hamzaoglu, M. Meterelliyoz, J. Keane, U. Bhattacharya, K. Zhang, K. Mistry, and M. Bohr. IEEE J. Solid State Circuits, 48 (1): 150-158 (2013)

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Shiraz Mistry

Mark Mistry

Taslim Mistry

Nouhad Ebrahim-Mistry

Savita Dullabh Mistry

Other publications of authors with the same name

8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET.P. Mishra, A. Tan, B. Helal, C. Ho, C. Loi, J. Riani, J. Sun, K. Mistry, K. Raviprakash, L. Tse and 18 other author(s). ISSCC, page 138-140. IEEE, (2021)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.E. Karl, Y. Wang, Y. Ng, Z. Guo, F. Hamzaoglu, M. Meterelliyoz, J. Keane, U. Bhattacharya, K. Zhang, K. Mistry and 1 other author(s). IEEE J. Solid State Circuits, 48 (1): 150-158 (2013)Keynote Address 1: "Transistors and reliability in the innovation era".K. Mistry. IRPS, page 1. IEEE, (2015)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.E. Karl, Y. Wang, Y. Ng, Z. Guo, F. Hamzaoglu, U. Bhattacharya, K. Zhang, K. Mistry, and M. Bohr. ISSCC, page 230-232. IEEE, (2012)Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends.S. Mathew, R. Krishnamurthy, M. Anders, R. Rios, K. Mistry, and K. Soumyanath. IEEE J. Solid State Circuits, 36 (11): 1636-1646 (2001)

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Disambiguation of "Mistry, Kaizad"

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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.

Please choose a person to relate this publication to

Shiraz Mistry

Mark Mistry

Taslim Mistry

Nouhad Ebrahim-Mistry

Savita Dullabh Mistry

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mistry, Kaizad"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.

Please choose a person to relate this publication to

Shiraz Mistry

Mark Mistry

Taslim Mistry

Nouhad Ebrahim-Mistry

Savita Dullabh Mistry

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.