%0 Journal Article %1 journals/tvlsi/SiddiquiLK21 %A Siddiqui, M. Sultan M. %A Lee, Zhao Chuan %A Kim, Tony Tae-Hyoung %D 2021 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 10 %P 1707-1719 %T A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#SiddiquiLK21 %V 29

@article{journals/tvlsi/SiddiquiLK21, added-at = {2022-03-16T00:00:00.000+0100}, author = {Siddiqui, M. Sultan M. and Lee, Zhao Chuan and Kim, Tony Tae-Hyoung}, biburl = {https://www.bibsonomy.org/bibtex/2c4f9fcb96ec05c0488dd9a1c734c637d/dblp}, ee = {https://www.wikidata.org/entity/Q108863229}, interhash = {d025739fd9accc9e64c3076fb6102d0e}, intrahash = {c4f9fcb96ec05c0488dd9a1c734c637d}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 10, pages = {1707-1719}, timestamp = {2024-04-08T14:31:34.000+0200}, title = {A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#SiddiquiLK21}, volume = 29, year = 2021 }