Author of the publication

A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (10): 1707-1719 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A novel analog-to-residue converter for biomedical DSP application., , , , and . ISOCC, page 371-374. IEEE, (2012)An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI., , , and . ESSCIRC, page 437-440. IEEE, (2016)An Automated System for Checking Lithography Friendliness of Standard Cells., , , , , and . APCCAS, page 261-265. IEEE, (2018)NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells., , , and . ISOCC, page 200-203. IEEE, (2012)Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints., , , , , , and . CoRR, (2018)An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI., , , and . IEEE J. Solid State Circuits, 54 (7): 2091-2101 (2019)0.2 V 8T SRAM with improved bitline sensing using column-based data randomization., , , , and . A-SSCC, page 141-144. IEEE, (2014)A System for Standard Cell Routability Checking and Placement Routability Improvements., , , , , and . APCCAS, page 125-128. IEEE, (2019)A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI., , and . A-SSCC, page 165-168. IEEE, (2017)0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization., , , , , and . IEEE J. Solid State Circuits, 51 (6): 1487-1498 (2016)