%0 Journal Article %1 journals/tcad/MarakkalageTRMS21 %A Marakkalage, Dewmini Sudara %A Testa, Eleonora %A Riener, Heinz %A Mishchenko, Alan %A Soeken, Mathias %A Micheli, Giovanni De %D 2021 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 10 %P 2184-2188 %T Three-Input Gates for Logic Synthesis. %U http://dblp.uni-trier.de/db/journals/tcad/tcad40.html#MarakkalageTRMS21 %V 40

@article{journals/tcad/MarakkalageTRMS21, added-at = {2023-07-27T00:00:00.000+0200}, author = {Marakkalage, Dewmini Sudara and Testa, Eleonora and Riener, Heinz and Mishchenko, Alan and Soeken, Mathias and Micheli, Giovanni De}, biburl = {https://www.bibsonomy.org/bibtex/2e8ee73700125825c59496661c6349e1a/dblp}, ee = {https://doi.org/10.1109/TCAD.2020.3032625}, interhash = {d5fac0251147ab6c4931e638dd6d621f}, intrahash = {e8ee73700125825c59496661c6349e1a}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 10, pages = {2184-2188}, timestamp = {2024-04-08T19:45:30.000+0200}, title = {Three-Input Gates for Logic Synthesis.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad40.html#MarakkalageTRMS21}, volume = 40, year = 2021 }