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Disambiguation of "Mishchenko, Alan"

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Three-Input Gates for Logic Synthesis.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)

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Oleksiy Mishchenko

Safwat Alani

Maia Alandjiyska

Yilmaz Alan

Viola Alanku

 

Other publications of authors with the same name

NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , and . BCB, page 623-624. ACM, (2014)Scalable min-register retiming under timing and initializability constraints., , and . DAC, page 534-539. ACM, (2008)Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)A Boolean Paradigm in Multi-Valued Logic Synthesis., and . IWLS, page 173-177. (2002)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , and . DATE, page 1649-1654. IEEE, (2019)Incremental ATPG methods for multiple faults under multiple fault models., , , and . ISQED, page 177-180. IEEE, (2015)Invariant-Strengthened Elimination of Dependent State Elements., , , , and . FMCAD, page 1-9. IEEE, (2008)Effective Logic Synthesis for Threshold Logic Circuit Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)Fast computation of symmetries in Boolean functions.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (11): 1588-1593 (2003)A theory of nondeterministic networks., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 977-999 (2006)