5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.
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%0 Journal Article
%1 journals/jssc/KulkarniKKNGKZ17
%A Kulkarni, Jaydeep P.
%A Keane, John
%A Koo, Kyung-Hoae
%A Nalam, Satyanand
%A Guo, Zheng
%A Karl, Eric
%A Zhang, Kevin
%D 2017
%J IEEE J. Solid State Circuits
%K dblp
%N 1
%P 229-239
%T 5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#KulkarniKKNGKZ17
%V 52
@article{journals/jssc/KulkarniKKNGKZ17,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Kulkarni, Jaydeep P. and Keane, John and Koo, Kyung-Hoae and Nalam, Satyanand and Guo, Zheng and Karl, Eric and Zhang, Kevin},
biburl = {https://www.bibsonomy.org/bibtex/281b8142f5ab6a2d59c628c7318f84cc3/dblp},
ee = {https://doi.org/10.1109/JSSC.2016.2607219},
interhash = {f07c1945a001b67985f619dccc04255d},
intrahash = {81b8142f5ab6a2d59c628c7318f84cc3},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 1,
pages = {229-239},
timestamp = {2020-08-31T11:42:47.000+0200},
title = {5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#KulkarniKKNGKZ17},
volume = 52,
year = 2017
}
