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%0 Conference Paper
%1 conf/glvlsi/ChengLDNW17
%A Cheng, Huimei
%A Li, Ji
%A Draper, Jeffrey T.
%A Nazarian, Shahin
%A Wang, Yanzhi
%B ACM Great Lakes Symposium on VLSI
%D 2017
%E Behjat, Laleh
%E Han, Jie
%E Velev, Miroslav N.
%E Chen, Deming
%I ACM
%K dblp
%P 427-430
%T Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.
%U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2017.html#ChengLDNW17
%@ 978-1-4503-4972-7
@inproceedings{conf/glvlsi/ChengLDNW17,
added-at = {2018-11-06T00:00:00.000+0100},
author = {Cheng, Huimei and Li, Ji and Draper, Jeffrey T. and Nazarian, Shahin and Wang, Yanzhi},
biburl = {https://www.bibsonomy.org/bibtex/27e02cd0b321a0f6116269873b7c2bb8a/dblp},
booktitle = {ACM Great Lakes Symposium on VLSI},
crossref = {conf/glvlsi/2017},
editor = {Behjat, Laleh and Han, Jie and Velev, Miroslav N. and Chen, Deming},
ee = {https://doi.org/10.1145/3060403.3060424},
interhash = {f5c3b0d38c304e3c0e7f5d7829be1d7b},
intrahash = {7e02cd0b321a0f6116269873b7c2bb8a},
isbn = {978-1-4503-4972-7},
keywords = {dblp},
pages = {427-430},
publisher = {ACM},
timestamp = {2018-11-07T13:01:39.000+0100},
title = {Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.},
url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2017.html#ChengLDNW17},
year = 2017
}