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Disambiguation of "Cheng, Huimei"

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Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.

, , , , and . ACM Great Lakes Symposium on VLSI, page 427-430. ACM, (2017)

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Cheng-Yung Cheng

Ying Min Cheng

I-Fen Cheng

Yao Cheng

Qing-Qi Cheng

 

Other publications of authors with the same name

Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design., , , , , , and . ASYNC, page 26-27. IEEE Computer Society, (2018)Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs., , , , and . ASYNC, page 85-93. IEEE Computer Society, (2017)SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol., , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (5): 1667-1677 (2020)Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (4): 979-992 (2022)Automatic Retiming of Two-Phase Latch-Based Resilient Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (7): 1305-1316 (2019)Area optimization of resilient designs guided by a mixed integer geometric program., , , and . DAC, page 130:1-130:6. ACM, (2016)Study on the influence of bus front-end intrusion-free distance to the bus moving characteristics., , and . Math. Comput. Simul., (2019)Yield modelling and analysis of bundled data and ring-oscillator based designs., , , , , and . IET Comput. Digit. Tech., 13 (3): 262-272 (2019)Area Optimization of Timing Resilient Designs Using Resynthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1197-1210 (2018)Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs., , , and . DATE, page 574-579. IEEE, (2020)