%0 Conference Paper %1 conf/vlsi/BeanatoLMLB12 %A Beanato, Giulia %A Loi, Igor %A Micheli, Giovanni De %A Leblebici, Yusuf %A Benini, Luca %B VLSI-SoC %D 2012 %E Katkoori, Srinivas %E Guthaus, Matthew R. %E Coskun, Ayse K. %E Burg, Andreas %E Reis, Ricardo %I IEEE %K dblp %P 30-35 %T 3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2012.html#BeanatoLMLB12 %@ 978-1-4673-2657-5

@inproceedings{conf/vlsi/BeanatoLMLB12, added-at = {2022-09-06T00:00:00.000+0200}, author = {Beanato, Giulia and Loi, Igor and Micheli, Giovanni De and Leblebici, Yusuf and Benini, Luca}, biburl = {https://www.bibsonomy.org/bibtex/2f2597eed2caf56d90934d6ae43c85f17/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2012soc}, editor = {Katkoori, Srinivas and Guthaus, Matthew R. and Coskun, Ayse K. and Burg, Andreas and Reis, Ricardo}, ee = {https://doi.org/10.1109/VLSI-SoC.2012.6379001}, interhash = {a6f0b61e95a7485f04764d6f5cd0116a}, intrahash = {f2597eed2caf56d90934d6ae43c85f17}, isbn = {978-1-4673-2657-5}, keywords = {dblp}, pages = {30-35}, publisher = {IEEE}, timestamp = {2024-04-09T12:01:32.000+0200}, title = {3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2012.html#BeanatoLMLB12}, year = 2012 }