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Disambiguation of "Giterman, Robert"

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Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 2180-2184 (2018)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Robert Wille

Towards a design flow for reversible logic. Uni Bremen, (2009)

Robert Klöfkorn

Numerics for evolution equations: a general interface based design concept. Uni Freiburg, (2009)

Robert Braun

Referenzmodellierung: Grundlegung und Evaluation der Technik des Modell-Konfigurationsmanagements. TU Dresden, (2010)

Robert Wagner

Inkrementelle Modellsynchronisation. Uni Paderborn, (2009)

Robert Zangenfeind

Das Bedeutung-Text-Modell: Wörterbuch und Grammatik einer integralen Sprachbeschreibung. Uni München, (2009)
 

Other publications of authors with the same name

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection., , and . IEEE Access, (2019)Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 358-362 (2016)Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space., , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1207-1217 (2020)Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros., , , , and . IEEE Access, (2021)Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique., , , and . ISCAS, page 1-5. IEEE, (2020)Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (4): 259-263 (2014)A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design., , , , and . ISCAS, page 1006-1009. IEEE, (2016)4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes., , , , and . ISCAS, page 2177-2180. IEEE, (2014)An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications., , , , , and . IEEE J. Solid State Circuits, 53 (7): 2136-2148 (2018)A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (4): 1245-1256 (2018)