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Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design.

, , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1683-1689 (March 2024)

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ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine., , and . DAC, page 1-6. IEEE, (2020)Accelerating graph computation with racetrack memory and pointer-assisted graph representation., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Memristor-based synapse design and a case study in reconfigurable systems., , , , and . IJCNN, page 1-6. IEEE, (2013)Array Organization and Data Management Exploration in Racetrack Memory., , , , and . IEEE Trans. Computers, 65 (4): 1041-1054 (2016)FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1167-1180 (2017)3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (2): 20:1-20:24 (2020)A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (8): 1353-1366 (2017)SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models., , , , , , , , , and . CoRR, (2023)SIO: Synthetic In-Distribution Data Benefits Out-of-Distribution Detection., , , , , and . CoRR, (2023)Spintronic Memristor: Compact Model and Statistical Analysis., , , and . J. Low Power Electron., 7 (2): 234-244 (2011)