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Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (12): 2855-2860 (2019)

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Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 109-119 (2011)Tunnel FET technology: A reliability perspective., , and . Microelectron. Reliab., 54 (5): 861-874 (2014)Computational paradigms using oscillatory networks based on state-transition devices., , , , and . IJCNN, page 3415-3422. IEEE, (2017)Ferroelectric Transistor based Non-Volatile Flip-Flop., , , , , and . ISLPED, page 10-15. ACM, (2016)Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells., , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 12 (4): 38:1-38:23 (2016)Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper)., , , , and . ICCAD, page 800-804. IEEE, (2017)On the potential of correlated materials in the design of spin-based cross-point memories (Invited)., , , and . ISCAS, page 1158-1161. IEEE, (2016)A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays., , , , , and . ASP-DAC, page 118-123. IEEE, (2015)Ferroelectrics: From Memory to Computing., , and . ASP-DAC, page 401-406. IEEE, (2020)FerroElectronics for Edge Intelligence., , , , and . IEEE Micro, 40 (6): 33-48 (2020)