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A 60Gbps DPI Prototype based on Memory-Centric FPGA.

J. Su, S. Chen, B. Han, C. Xu, and X. Wang. SIGCOMM, page 627-628. ACM, (2016)

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Chengcheng Wang

Xu Xu

Chengcheng Christine Zhang

Other publications of authors with the same name

A 60Gbps DPI Prototype based on Memory-Centric FPGA.J. Su, S. Chen, B. Han, C. Xu, and X. Wang. SIGCOMM, page 627-628. ACM, (2016)UniTSA: A Universal Reinforcement Learning Framework for V2X Traffic Signal Control.M. Wang, X. Xiong, Y. Kan, C. Xu, and M. Pun. CoRR, (2023)A Three-Wafer-Stacked Hybrid 15-MPixel CIS + 1-MPixel EVS With 4.6-GEvent/s Readout, In-Pixel TDC, and On-Chip ISP and ESP Function.M. Guo, S. Chen, Z. Gao, W. Yang, P. Bartkovjak, Q. Qin, X. Hu, D. Zhou, Q. Huang, M. Uchiyama and 12 other author(s). IEEE J. Solid State Circuits, 58 (11): 2955-2964 (November 2023)Multi-Antenna Joint Radar and Communications: Precoder Optimization and Weighted Sum-Rate vs Probing Power Tradeoff.C. Xu, B. Clerckx, and J. Zhang. IEEE Access, (2020)Efficient focused energy delivery with grating lobe mitigation for precision electronic warfare.S. Chen, C. Xu, and J. Zhang. Signal Process., (2020)Reinforcement Learning-Based Variable Speed Limits Control to Reduce Crash Risks Near Traffic Oscillations on Freeways.Z. Li, C. Xu, Y. Guo, P. Liu, and Z. Pu. IEEE Intell. Transp. Syst. Mag., 13 (4): 64-70 (2021)Rate-Splitting Multiple Access for Multi-Antenna Joint Radar and Communications.C. Xu, B. Clerckx, S. Chen, Y. Mao, and J. Zhang. CoRR, (2021)Efficient Distributed Method for NLOS Cooperative Localization in WSNs.S. Chen, J. Zhang, Y. Mao, C. Xu, and Y. Gu. Sensors, 19 (5): 1173 (2019)Strong Tracking Current Statistical Model Based on Mixed Bayesian-Fisher Model.S. Bao, S. Cheng, and C. Xu. CRC, page 75-79. IEEE, (2017)Development of analytical procedure for selection of control measures to reduce congestions at various freeway bottlenecks.Z. Li, P. Liu, C. Xu, and W. Wang. J. Intell. Transp. Syst., 22 (1): 65-85 (2018)

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Disambiguation of "Xu, Chengcheng"

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A 60Gbps DPI Prototype based on Memory-Centric FPGA.

Please choose a person to relate this publication to

Chengcheng Wang

Chengcheng Wang

Xu Xu

Xu Xu

Chengcheng Christine Zhang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xu, Chengcheng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 60Gbps DPI Prototype based on Memory-Centric FPGA.

Please choose a person to relate this publication to

Chengcheng Wang

Chengcheng Wang

Xu Xu

Xu Xu

Chengcheng Christine Zhang

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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A 60Gbps DPI Prototype based on Memory-Centric FPGA.