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Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications., , , и . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2476-2487 (2014)BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 90-103 (2023)Data Remapping for Static NUCA in Degradable Chip Multiprocessors., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 879-892 (2015)Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects., , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1787-1800 (2011)Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 92-102 (2016)DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning., , , , , и . J. Supercomput., 79 (3): 2819-2849 (2023)Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs., , , и . IEEE Trans. Very Large Scale Integr. Syst., 21 (2): 239-249 (2013)Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes., , , и . IEEE Trans. Instrum. Meas., 55 (2): 389-399 (2006)New Methodologies for Parallel Architecture., , и . J. Comput. Sci. Technol., 26 (4): 578-587 (2011)A Novel Post-Silicon Debug Mechanism Based on Suspect Window., , и . IEICE Trans. Inf. Syst., 93-D (5): 1175-1185 (2010)