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Test Resource Partitioning for System-on-a-Chip.

, , and . Frontiers in electronic testing Kluwer / Springer, (2002)

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Designing effective scan compression solutions for industrial circuits., , and . ISQED, page 167-172. IEEE, (2015)Response compaction for system-on-a-chip based on advanced convolutional codes., , , and . Sci. China Ser. F Inf. Sci., 49 (2): 262-272 (2006)Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores., , , , , and . IEICE Trans. Inf. Syst., 88-D (9): 2126-2134 (2005)Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)., , and . Asian Test Symposium, page 432-437. IEEE Computer Society, (2011)Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste., , , , and . Asian Test Symposium, page 440-445. IEEE Computer Society, (2003)Test data compression and decompression based on internal scanchains and Golomb coding., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (6): 715-722 (2002)Proactive management of X's in scan chains for compression., , and . ISQED, page 260-265. IEEE Computer Society, (2009)Interval Based X-Masking for Scan Compression Architectures., and . ISQED, page 821-826. IEEE Computer Society, (2008)Test Resource Partitioning for System-on-a-Chip., , and . Frontiers in electronic testing Kluwer / Springer, (2002)Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters., , and . VLSI Design, 12 (4): 475-486 (2001)