( en | de | ru )

 

Disambiguation of "Kotásek, Zdenek"

Author of the publication

copydeleteadd this publication to your clipboard
Polymorphic Gates in Design and Test of Digital Circuits.

, , , and . Int. J. Unconv. Comput., 4 (2): 125-142 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Zdenek Filip

Zdenek Cerman

Zdenek Cerny

Zdenek amrda

Zdenek Por

 

Other publications of authors with the same name

The Identification of registers in RTL Structures for the Test Application., , and . ISoLA (Preliminary proceedings), volume TR-2004-6 of Technical Report, page 317-319. Department of Computer Science, University of Cyprus, (2004)Automated Functional Verification of Application Specific Instruction-set Processors., , , and . IESS, volume 403 of IFIP Advances in Information and Communication Technology, page 128-138. Springer, (2013)pecial CAI Section Devoted to MEMICS '11: Preface., , , , and . Comput. Informatics, 31 (3): 481- (2012)Evolution of synthetic RTL benchmark circuits with predefined testability., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 54:1-54:21 (2008)Fault tolerant Field Programmable Neural Networks., , and . NORCAS, page 1-4. IEEE, (2015)Testability analysis based on the identification of testable blocks with predefined properties., , and . Microprocess. Microsystems, 32 (5-6): 296-302 (2008)Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis., , and . EWDTS, page 1-7. IEEE, (2018)Preface., , , , and . MEMICS, volume 251 of Electronic Notes in Theoretical Computer Science, page 1-3. Elsevier, (2008)Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA., and . DDECS, page 171-174. IEEE Computer Society, (2014)Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study., , , , , and . DSD, page 597-600. IEEE, (2019)