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Disambiguation of "Chandrachoodan, Nitin"

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The hierarchical timing pair model for multirate DSP applications.

, , and . IEEE Trans. Signal Process., 52 (5): 1209-1217 (2004)

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Sirin Nitinawarat

Nitin Nangare

Nitin Suresh

Nitin Kaskhedikar

Nitin Jain

 

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Interconnect Aware Test Power Reduction., , and . J. Low Power Electron., 8 (4): 516-525 (2012)EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA., , and . FCCM, page 242. IEEE, (2020)Guided multilevel approximation of less significant bits for power reduction., and . VDAT, page 1-6. IEEE, (2016)Layerwise Disaggregated Evaluation of Spiking Neural Networks., , , and . ISLPED, page 25:1-25:6. ACM, (2022)Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA., and . ICIIS, page 1-4. IEEE, (2008)Split-Knit Convolution: Enabling Dense Evaluation of Transpose and Dilated Convolutions on GPUs., , , and . HIPC, page 1-10. IEEE, (2022)Optimizing power-accuracy trade-off in approximate adders., , and . DATE, page 1488-1491. IEEE, (2018)Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization., , , , and . DAC, page 182:1-182:7. ACM, (2013)Designing a passive star optical network for the India-based Neutrino Observatory., , and . NCC, page 1-6. IEEE, (2015)FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only)., , , and . FPGA, page 295. ACM, (2017)