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Redefining the Role of the CPU in the Era of CPU-GPU Integration., , , , and . IEEE Micro, 32 (6): 4-16 (2012)Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes., and . ISPD, page 83-90. ACM, (2021)BufFormer: A Generative ML Framework for Scalable Buffering., , , , and . ASP-DAC, page 264-270. ACM, (2023)Generative self-supervised learning for gate sizing: invited., , , , , and . DAC, page 1331-1334. ACM, (2022)Optimal reliability-constrained overdrive frequency selection in multicore systems., and . ISQED, page 300-308. IEEE, (2014)Incremental multiple-scan chain ordering for ECO flip-flop insertion., , and . ICCAD, page 705-712. IEEE, (2013)TransSizer: A Novel Transformer-Based Fast Gate Sizer., , , , , and . ICCAD, page 74:1-74:9. ACM, (2022)A Fast Learning-Driven Signoff Power Optimization Framework., , , and . ICCAD, page 161:1-161:9. IEEE, (2020)RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning., , , and . DAC, page 733-738. IEEE, (2021)Enhanced metamodeling techniques for high-dimensional IC design estimation problems., , and . DATE, page 1861-1866. EDA Consortium San Jose, CA, USA / ACM DL, (2013)