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Disambiguation of "Masui, Shoichi"

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Radio channel characterization for 400 MHz implanted devices.

, , , , , , , and . WCNC, page 293-298. IEEE, (2014)

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Shoichi Watanabe

 

Other publications of authors with the same name

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology., , , , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 101-110 (2007)A ferroelectric memory-based secure dynamically programmable gate array., , , , , and . IEEE J. Solid State Circuits, 38 (5): 715-725 (2003)Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL., , and . IEICE Trans. Electron., 94-C (6): 1065-1068 (2011)Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm., , , and . IEICE Trans. Electron., 88-C (4): 576-581 (2005)A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology., , , , , , , , , and . ISSCC, page 1201-1210. IEEE, (2006)Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers., , , and . IEICE Trans. Electron., 92-C (10): 1304-1310 (2009)An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI., , , , , , , and . A-SSCC, page 265-268. IEEE, (2014)Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (8): 1337-1346 (2012)Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology., , , , , and . IEICE Trans. Electron., 94-C (3): 334-345 (2011)An area-efficient universal cryptography processor for smart cards., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (1): 43-56 (2006)