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Disambiguation of "Portal, Jean-Michel"

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Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.

, , , , , , , and . NANOARCH, page 1-5. IEEE, (2019)

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Jean-Michel Langlais

Jean-Michel Dengler

Jean-Michel Grossenbacher

Jean-Michel Autebert

Jean-Michel Ayache

 

Other publications of authors with the same name

Testing the Local Interconnect Resources of SRAM-Based FPGA's., , , and . J. Electron. Test., 16 (5): 513-520 (2000)Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications., , , , , , , , and . CoRR, (2020)Implementation of Ternary Weights with Resistive RAM Using a Single Sense Operation per Synapse., , , , , , , and . CoRR, (2020)Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell., , , , , , , , , and 6 other author(s). CoRR, (2023)Stochastic Computing for Hardware Implementation of Binarized Neural Networks., , , , , and . CoRR, (2019)Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology., , , , , , , , , and 2 other author(s). MWSCAS, page 897-900. IEEE, (2014)CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks., , , , , , , , and . MWSCAS, page 158-161. IEEE, (2021)A Novel Low Power Oriented Design Methodology for Analog Blocks., , , and . J. Low Power Electron., 4 (1): 60-67 (2008)Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks., , , , , , , , and . CoRR, (2021)Memory-Centric Neuromorphic Computing With Nanodevices., , , , , , , , , and . BioCAS, page 1-4. IEEE, (2019)