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Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop.

, , , and . J. Low Power Electron., 10 (1): 149-162 (2014)

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A Schmitt trigger to benchmark the performance of a new zero-cost transistor., , , , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)40nm SONOS Embedded Select in Trench Memory., , , , , , , , , and 3 other author(s). ESSDERC, page 21-24. IEEE, (2023)Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology., , , , , , , , , and 1 other author(s). DTIS, page 1-5. IEEE, (2021)Reconfiguration time overhead on field programmable gate arrays: reduction and cost model., , and . IET Comput. Digit. Tech., 6 (2): 105-113 (2012)Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop., , , and . J. Low Power Electron., 10 (1): 149-162 (2014)Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor., , , , , , , and . ISCAS, page 761-764. IEEE, (2022)VCO design in SOI technologies., , , , and . NEWCAS, page 420-423. IEEE, (2014)Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology., , , , , and . J. Low Power Electron., 12 (1): 64-73 (2016)