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Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.

D. Novo, R. Fasthuber, P. Raghavan, A. Bourdoux, M. Li, L. der Perre, and F. Catthoor. SiPS, page 151-156. IEEE, (2009)

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Energy efficient FFT implementation through stage skipping and merging.N. Sharma, P. Panda, and F. Catthoor. CODES+ISSS, page 153-162. IEEE, (2015)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.M. Komalan, O. Rock, M. Hartmann, S. Sakhare, C. Tenllado, J. Gómez, G. Kar, A. Furnémont, F. Catthoor, S. Senni and 3 other author(s). DATE, page 103-108. IEEE, (2018)Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices.D. Atienza, M. Leeman, F. Catthoor, G. Deconinck, J. Mendias, V. Florio, and R. Lauwereins. ICME, page 803-806. IEEE Computer Society, (2004)System scenario framework evaluation on EFM32 using the H264/AVC encoder control structure.Y. Yassin, P. Kjeldsberg, and F. Catthoor. ECCTD, page 1-4. IEEE, (2015)Analysis of scratch-pad and data-cache performance using statistical methods.J. Absar, and F. Catthoor. ASP-DAC, page 820-825. IEEE, (2006)Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.I. Taniguchi, M. Jayapala, P. Raghavan, F. Catthoor, K. Sakanushi, Y. Takeuchi, and M. Imai. ASP-DAC, page 449-454. IEEE, (2009)Towards high-performance polarity-controllable FETs with 2D materials.G. Resta, J. Gonzalez, Y. Balaji, T. Agarwal, D. Lin, F. Catthoor, I. Radu, G. Micheli, and P. Gaillardon. DATE, page 637-641. IEEE, (2018)Degradation analysis of high performance 14nm FinFET SRAM.D. Kraak, I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, and F. Catthoor. DATE, page 201-206. IEEE, (2018)Finite precision processing in wireless applications.D. Novo, M. Li, B. Bougard, L. der Perre, and F. Catthoor. DATE, page 1230-1233. IEEE, (2009)Data memory optimization in LTE downlink.N. Sharma, T. Aa, P. Agrawal, P. Raghavan, P. Panda, and F. Catthoor. ICASSP, page 2610-2614. IEEE, (2013)

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Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.

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Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.