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Disambiguation of "David, Jean-Pierre"

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BinaryConnect: Training Deep Neural Networks with binary weights during propagations.

, , and . NIPS, page 3123-3131. (2015)

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Jean-Pierre Mazat

Pierre Jean Regenet

Jean Pierre Calteux

Jean-Pierre Dubost

Jean-Pierre Détry

 

Other publications of authors with the same name

Ultra-low latency communication channels for FPGA-based HPC cluster., and . Integr., (2018)Analytical model for multi-junction solar cells prediction in space environment., , and . Microelectron. Reliab., 48 (8-9): 1494-1499 (2008)Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique., , , , , , and . IEEE Trans. Circuits Syst., 67-I (11): 3978-3990 (2020)Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation., , , and . ACM Trans. Reconfigurable Technol. Syst., 4 (2): 12:1-12:27 (2011)An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters., , and . IEEE Trans. Ind. Electron., 65 (1): 636-644 (2018)A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits., , , , and . Math. Comput. Simul., (2013)Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference., , , , , , and . NEWCAS, page 1-5. IEEE, (2023)Effective floating-point calculation engines intended for the FPGA-based HIL simulation., , , , and . ISIE, page 1363-1368. IEEE, (2012)An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices., , , , and . ISCAS, page 2529-2533. IEEE, (2022)Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications., , , and . IPDPS, page 143. IEEE Computer Society, (2001)