Author of the publication

Design in the nano-scale Era: Low-power, reliability, and error resiliency.

. SoCC, page 445. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Novel Approach to Accurate Timing Verification Using RTL Descriptions., and . DAC, page 638-641. ACM Press, (1989)Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits., , , , and . DAC, page 489-494. ACM Press, (1998)Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems., , and . CoRR, (2015)Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits, , and . CoRR, (2007)All-Photonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light., , , and . CoRR, (2018)Image Edge Detection based on Swarm Intelligence using Memristive Networks., and . CoRR, (2016)FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition., , , and . CoRR, (2016)Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies, , , , and . CoRR, (2007)STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks., , , and . CoRR, (2014)Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars., , and . CoRR, (2017)