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The nuts and bolts of physical synthesis.

, , , , , , , , и . SLIP, стр. 89-94. ACM, (2007)

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Aman K K Bhasin

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Fast estimation of area-delay trade-offs in circuit sizing., и . ISCAS (4), стр. 3575-3578. IEEE, (2005)Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 45-58 (2008)Logical effort based technology mapping., и . ICCAD, стр. 419-422. IEEE Computer Society / ACM, (2004)Fast Electrical Correction Using Resizing and Buffering., , , , , и . ASP-DAC, стр. 553-558. IEEE Computer Society, (2007)The nuts and bolts of physical synthesis., , , , , , , , и . SLIP, стр. 89-94. ACM, (2007)Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect., и . DAC, стр. 377-382. ACM, (2001)FIRA - a novel method for benchmarking the cache hierarchy., , и . COMPUTE, стр. 14. ACM, (2012)Fast Comparisons of Circuit Implementations., и . DATE, стр. 910-915. IEEE Computer Society, (2004)Fast comparisons of circuit implementations., и . IEEE Trans. Very Large Scale Integr. Syst., 13 (12): 1329-1339 (2005)Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect., и . IEEE Trans. Very Large Scale Integr. Syst., 11 (6): 1094-1105 (2003)