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A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors.

, , , , , , and . ACM Trans. Comput. Syst., 30 (2): 8:1-8:38 (2012)

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A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors., , , , , , and . ACM Trans. Comput. Syst., 30 (2): 8:1-8:38 (2012)A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , and . PACT, page 77-87. IEEE Computer Society, (2009)A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , and . IEEE Micro, 30 (1): 29-39 (2010)GoldMine: Automatic assertion generation using data mining and static analysis., , , , , and . DATE, page 626-629. IEEE Computer Society, (2010)GPU Subwarp Interleaving., , , , , and . HPCA, page 1184-1197. IEEE, (2022)Tradeoffs in designing accelerator architectures for visual computing., , , and . MICRO, page 164-175. IEEE Computer Society, (2008)Speculative reconvergence for improved SIMT efficiency., , , , , , and . CGO, page 121-132. ACM, (2020)Rigel: an architecture and scalable programming interface for a 1000-core accelerator., , , , , , , , and . ISCA, page 140-151. ACM, (2009)Architecting an Energy-Efficient DRAM System for GPUs., , , , , , and . HPCA, page 73-84. IEEE Computer Society, (2017)A variable warp size architecture., , , and . ISCA, page 489-501. ACM, (2015)