Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

General switch box modeling and optimization for FPGA routing architectures., , , , and . FPT, page 320-323. IEEE, (2010)An on-line debug method for FPGAs., , and . ASICON, page 484-487. IEEE, (2017)High performance Deformable Part Model accelerator based on FPGA., , , , , and . FPT, page 245-248. IEEE, (2016)Fast Adjustable NPN Classification using Generalized Symmetries., , , and . FPL, page 1-7. IEEE Computer Society, (2018)A scalable hybrid architecture for high performance data-parallel applications., , , , , and . FPT, page 191-194. IEEE, (2017)An automated test framework for SRAM-based FPGA., , , and . ASICON, page 1-4. IEEE, (2015)An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis., , , and . ACM Trans. Design Autom. Electr. Syst., 29 (2): 25:1-25:33 (März 2024)Online Task Scheduling for Heterogeneous Reconfigurable Systems., , , and . CSCWD (Selected Papers), volume 5236 of Lecture Notes in Computer Science, page 596-607. Springer, (2007)Automatic layout generator for embedded FPGA cores., , and . ASICON, page 385-388. IEEE, (2011)SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (12): 2179-2192 (2013)