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Disambiguation of "Sinanoglu, Ozgur"

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$PoisonedGNN$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems.

, , , , and . IEEE Trans. Computers, 72 (10): 2822-2834 (October 2023)

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Nalan Sinanoglu

Hakan Sinanoglu

Soner Özgür

Nevzat Özgür

Sevim Özgür

 

Other publications of authors with the same name

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime., , , , and . CoRR, (2019)A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects., , , and . CoRR, (2019)ScanSAT: Unlocking Static and Dynamic Scan Obfuscation., , , , , , and . CoRR, (2019)Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (9): 1740-1753 (2021)Testing Chips With Spare Identical Cores., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (7): 1124-1135 (2013)Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (2): 266-280 (2022)Logic Locking With Provable Security Against Power Analysis Attacks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (4): 766-778 (2020)Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 822-834 (2015)Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (2): 298-302 (2009)Isolation Techniques for Soft Cores., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1453-1466 (2008)