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Disambiguation of "Pogiel, Artur"

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High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.

, , , , , , and . ATS, page 74-80. IEEE Computer Society, (2014)

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Artur Teuscher

Artur Budnowski

Artur Schüler

Artur Schütz

Artur Spering

 

Other publications of authors with the same name

Fault diagnosis for embedded read-only memories., , , and . ITC, page 1-10. IEEE Computer Society, (2009)High Volume Diagnosis in Memory BIST Based on Compressed Failure Data., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 441-453 (2010)High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST., , , and . ITC, page 1-10. IEEE Computer Society, (2008)Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs., , , , , and . J. Electron. Test., 27 (5): 599-609 (2011)Diagnosis of failing scan cells through orthogonal response compaction., , , , , and . European Test Symposium, page 221-226. IEEE Computer Society, (2010)LBIST for Automotive ICs With Enhanced Test Generation., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2290-2300 (2022)High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs., , , , , , and . ATS, page 74-80. IEEE Computer Society, (2014)Quality assurance in memory built-in self-test tools., , , , , and . DDECS, page 39-44. IEEE Computer Society, (2014)ROM fault diagnosis for O(n2) test algorithms., , and . ETS, page 1-6. IEEE, (2017)Fault Diagnosis With Convolutional Compactors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (8): 1478-1494 (2007)