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Disambiguation of "Shimada, Toshio"

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A priority forwarding scheme for real-time multistage interconnection networks.

, , , and . RTSS, page 208-217. IEEE Computer Society, (1992)

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Shingo Shimada

Toshio Kawai

Ryusuke Shimada

Toshio Tsuzuki

Toshio Kuroda

 

Other publications of authors with the same name

Sequential description and parallel execution language DFCII dataflow supercomputers., , and . ICS, page 57-66. ACM, (1991)Power consumption reduction scheme focusing on the Depth of Speculative Execution., , , and . CIT, page 207-212. IEEE Computer Society, (2008)A priority forwarding scheme for real-time multistage interconnection networks., , , and . RTSS, page 208-217. IEEE Computer Society, (1992)Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors., , , and . ICPP, page 584-591. IEEE Computer Society Press, (1986)The Hardware Architecture of the CODA Real-Time Parallel Processor., , , and . PARCO, page 395-402. Elsevier, (1993)A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 34 (11): 1619-1626 (1999)Efficient vector processing on dataflow supercomputer SIGMA-1., , and . SC, page 374-381. IEEE Computer Society, (1988)Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations., , , and . ISCA, page 226-234. IEEE Computer Society, (1986)An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism., , , , and . EUROMICRO, page 1432-1440. IEEE Computer Society, (1999)A preactivating mechanism for a VT-CMOS cache using address prediction., , , , and . ISLPED, page 247-250. ACM, (2002)