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OpenMDSP: Extending OpenMP to Program Multi-Core DSPs.

, , , , , and . J. Comput. Sci. Technol., 29 (2): 316-331 (2014)

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URPR-1: A single-chip VLIW architecture., , , , and . Microprocess. Microprogramming, 39 (1): 25-41 (1993)Optimization of frequent itemset mining on multiple-core processor, , , and . VLDB '07: Proceedings of the 33rd international conference on Very large data bases, page 1275--1285. VLDB Endowment, (2007)Multilevel Pattern Matching Architecture for Network Intrusion Detection and Prevention System., , and . ICESS, volume 4523 of Lecture Notes in Computer Science, page 604-614. Springer, (2007)OpenMDSP: Extending OpenMP to Program Multi-Core DSPs., , , , , and . J. Comput. Sci. Technol., 29 (2): 316-331 (2014)A software pipelining based VLIW architecture and optimizing compiler., , , , and . MICRO, page 17-27. ACM/IEEE, (1990)Increasing Software-Pipelined Loops in the Itanium-Like Architecture., , , and . ISPA, volume 3358 of Lecture Notes in Computer Science, page 947-951. Springer, (2004)NestedMP: Taming Complex Configuration Space of Degree of Parallelism for Nested-Parallel Programs., , and . ICPP Workshops, page 339-348. IEEE Computer Society, (2014)OpenMDSP: Extending OpenMP to Program Multi-Core DSP., , , , , and . PACT, page 288-297. IEEE Computer Society, (2011)Understanding the Memory Behavior of Emerging Multi-core Workloads., , , , and . ISPDC, page 153-160. IEEE Computer Society, (2009)Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures., , and . J. Low Power Electron., 8 (2): 146-157 (2012)