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A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction., , and . Comput. J., 50 (5): 616-628 (2007)High performance Viterbi decoder using modified register exchange methods., , and . ISCAS (3), page 553-556. IEEE, (2004)Design of eMMC controller with multiple channels., and . ISOCC, page 317-318. IEEE, (2016)A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 59 (4): 1216-1224 (April 2024)PBP-Net: Point Projection and Back-Projection Network for 3D Point Cloud Segmentation., , , , , and . IROS, page 8469-8475. IEEE, (2020)A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Projection-based Point Convolution for Efficient Point Cloud Segmentation., , , , and . CoRR, (2022)Asymptotics of a class of pth-order nonlinear autoregressive processes. Statistics & Probability Letters, 40 (2): 171--177 (Sep 15, 1998)Design of a programmable cryptoprocessor for multiple cryptosystems., , , and . SoCC, page 157-158. IEEE, (2004)Design of Light-Weight High-Entropy Alloys., , , , , , , , and . Entropy, 18 (9): 333 (2016)