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Disambiguation of "Saluja, Kewal K."

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Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.

, , , , and . Asian Test Symposium, page 242-247. IEEE Computer Society, (2002)

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Heinz Kewald

Kewal Krishen Mehta

Aman K K Bhasin

K Schaber

K Beheng

 

Other publications of authors with the same name

Testing Computer Hardware through Data Compression in Space and Time., and . ITC, page 83-88. IEEE Computer Society, (1983)Modified T-Flip-Flop based scan cell for RAS., , , , and . European Test Symposium, page 113-118. IEEE Computer Society, (2010)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment., , , and . IEICE Trans. Inf. Syst., 96-D (6): 1323-1331 (2013)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , and . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)Routing TCP Flows in Underwater Mesh Networks., , and . IEEE J. Sel. Areas Commun., 29 (10): 2022-2032 (2011)A Tutorial on Built-In Self-Test, Part 2: Applications., , and . IEEE Des. Test Comput., 10 (2): 69-77 (1993)Efficient Test Set Modification for Capture Power Reduction., , , , , , and . J. Low Power Electron., 1 (3): 319-330 (2005)Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling., and . J. Electron. Test., 30 (5): 569-580 (2014)An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)