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Disambiguation of "Ranganathan, Sudarsan V. S."

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Serial List Viterbi Decoding with CRC: Managing Errors, Erasures, and Complexity.

, , and . GLOBECOM, page 1-6. IEEE, (2018)

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Hiranmayi Ranganathan

Suresh Sudarsan

V Geoffroy

V Saile

V Adams

 

Other publications of authors with the same name

Linear Rate-Compatible Codes with Degree-1 Extending Variable Nodes Under Iterative Decoding., , and . ISIT, page 1166-1170. IEEE, (2018)Allocating Redundancy Between Erasure Coding and Channel Coding When Fading Channel Diversity Grows With Codeword Length., , and . IEEE Trans. Commun., 65 (8): 3226-3237 (2017)Design of improved quasi-cyclic protograph-based Raptor-like LDPC codes for short block-lengths., , and . ISIT, page 1207-1211. IEEE, (2017)Serial List Viterbi Decoding with CRC: Managing Errors, Erasures, and Complexity., , and . GLOBECOM, page 1-6. IEEE, (2018)Decoding Flash Memory with Progressive Reads and Independent vs. Joint Encoding of Bits in a Cell., , , , and . GLOBECOM, page 1-6. IEEE, (2019)Optimality and Rate-Compatibility for Erasure-Coded Packet Transmissions when Fading Channel Diversity Increases with Packet Length., , and . CoRR, (2016)Approaching capacity using incremental redundancy without feedback., , and . ISIT, page 161-165. IEEE, (2017)An information density approach to analyzing and optimizing incremental redundancy with feedback., , , , , , and . ISIT, page 261-265. IEEE, (2017)On the girth of (3, L) quasi-cyclic LDPC codes based on complete protographs., , and . ISIT, page 431-435. IEEE, (2015)Variable-Length Coding With Shared Incremental Redundancy: Design Methods and Examples., , and . IEEE Trans. Commun., 67 (9): 5981-5995 (2019)