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« Faites de votre passion un métier » ; Etsy, une plateforme d’émancipation féminine ?

. La Nouvelle Revue du Travail, (July 2018)
DOI: 10.4000/nrt.3870

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« Faites de votre passion un métier » ; Etsy, une plateforme d’émancipation féminine ?. La Nouvelle Revue du Travail, (July 2018)MEMS packaging and reliability: An undividable couple., , , , , , , , , and 1 other author(s). Microelectron. Reliab., 52 (9-10): 2228-2234 (2012)Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 330-331. IEEE, (2022)Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 429-430. IEEE, (2022)Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding., , , , , , , , , and 6 other author(s). 3DIC, page 1-4. IEEE, (2011)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 431-432. IEEE, (2022)300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications., , , , , , , , , and . 3DIC, page 1-4. IEEE, (2010)Extreme wafer thinning optimization for via-last applications., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2016)Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)