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WCET analysis of instruction cache hierarchies., and . J. Syst. Archit., 57 (7): 677-694 (2011)Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors., , and . ECRTS, volume 76 of LIPIcs, page 14:1-14:22. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2017)SAMVA: Static Analysis for Multi-fault Attack Paths Determination., , , and . COSADE, volume 13979 of Lecture Notes in Computer Science, page 3-22. Springer, (2023)Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems., , , , , and . ECRTS, page 262-272. IEEE Computer Society, (2016)The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults., , , and . MICRO, page 48-59. IEEE Computer Society, (2012)Speeding up Static Probabilistic Timing Analysis., , , , , and . ARCS, volume 9017 of Lecture Notes in Computer Science, page 236-247. Springer, (2015)On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques., , , , and . ECRTS, page 266-275. IEEE Computer Society, (2014)Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches., , and . RTSS, page 68-77. IEEE Computer Society, (2009)Optimizing Data-Center TCO with Scale-Out Processors., , , , , and . IEEE Micro, 32 (5): 52-63 (2012)Static probabilistic worst case execution time estimation for architectures with faulty instruction caches., and . Real Time Syst., 51 (2): 128-152 (2015)