( en | de | ru )

 

Disambiguation of "DeMara, Ronald F."

Author of the publication

copydeleteadd this publication to your clipboard
Sustainability assurance modeling for SRAM-based FPGA evolutionary self-repair.

, , , and . ICES, page 17-22. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ronald Keipert

Acmella ciliata (H.B.K.) Cassini: phytochemische und enzymatische Untersuchungen, galenische Präformulierungen. FU Berlin, (2009)

F Georgi

F Himmel

F Arndt

F Röpke

 

Other publications of authors with the same name

Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms., and . Appl. Soft Comput., 12 (8): 2470-2480 (2012)SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks., and . CoRR, (2019)Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons., , , and . CoRR, (2018)Data-partitioning using the Hilbert space filling curves: Effect on the speed of convergence of Fuzzy ARTMAP for large database problems., , , and . Neural Networks, 18 (7): 967-984 (2005)Progress in autonomous fault recovery of field programmable gate arrays., , and . ACM Comput. Surv., 43 (4): 31:1-31:30 (2011)Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices., , and . ISQED, page 49-54. IEEE, (2018)Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing., , , and . IET Circuits Devices Syst., 11 (3): 274-279 (2017)Electrically-Tunable Stochasticity for Spin-based Neuromorphic Circuits: Self-Adjusting to Variation., , , , and . MWSCAS, page 81-84. IEEE, (2020)Optimization of NULL convention self-timed circuits., , , , and . Integr., 37 (3): 135-165 (2004)Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (7): 678-682 (2016)