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Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization., and . ISLPED, page 326-331. ACM, (2004)Reducing Exit Stub Memory Consumption in Code Caches., , and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 87-101. Springer, (2007)Exploiting Parallelism Opportunities with Deep Learning Frameworks., , , , and . ACM Trans. Archit. Code Optim., 18 (1): 9:1-9:23 (2021)The Architectural Implications of Facebook's DNN-based Personalized Recommendation., , , , , , , , , and 5 other author(s). CoRR, (2019)Sustainable AI: Environmental Implications, Challenges and Opportunities., , , , , , , , , and 15 other author(s). CoRR, (2021)Code Cache Management Schemes for Dynamic Optimizers., and . Interaction between Compilers and Computer Architectures, page 102-110. IEEE Computer Society, (2002)Adaptive Online Context-Sensitive Inlining., and . CGO, page 253-264. IEEE Computer Society, (2003)EcoSim: a language and experience teaching parallel programming in elementary school., , , and . SIGCSE, page 51-56. ACM, (2012)Where is the data? Why you cannot debate CPU vs. GPU performance without the answer., and . ISPASS, page 134-144. IEEE Computer Society, (2011)Datacenter-Scale Analysis and Optimization of GPU Machine Learning Workloads., , , , , , , , , and 3 other author(s). IEEE Micro, 41 (5): 101-112 (2021)