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Disambiguation of "Ciesielski, Maciej J."

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BDD Decomposition for Efficient Logic Synthesis.

, , and . ICCD, page 626-. IEEE Computer Society, (1999)

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Christian Ciesielski

Mechthild Ciesielski

Thomas Ciesielski

Richard Ciesielski

Axel Ciesielski

 

Other publications of authors with the same name

Placement for Clock Period Minimization With Multiple Wave Propagation., and . DAC, page 640-643. ACM, (1991)BDS: a BDD-based logic optimization system., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (7): 866-876 (2002)Clock period minimization with wave pipelining., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (4): 461-472 (1993)Optimizing data flow graphs to minimize hardware implementation., , , , and . DATE, page 117-122. IEEE, (2009)High-Level Dataflow Transformations Using Taylor Expansion Diagrams., , , and . IEEE Des. Test Comput., 26 (4): 46-57 (2009)Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future.. DSD, page xxxiv. IEEE, (2023)Efficient factorization of DSP transforms using taylor expansion diagrams., , , , , and . DATE, page 754-755. European Design and Automation Association, Leuven, Belgium, (2006)Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning., and . ISVLSI, page 619-624. IEEE Computer Society, (2014)Exploiting Circuit Duality to Speed up SAT., , , , and . ISVLSI, page 101-106. IEEE Computer Society, (2015)Data-flow transformations using Taylor expansion diagrams., , , , and . DATE, page 455-460. EDA Consortium, San Jose, CA, USA, (2007)