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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder., , , , and . ASICON, page 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems., , , , and . ISCAS, page 1516-1519. IEEE, (2012)Low-complexity two-stage timing acquisition scheme for UWB communications., , and . WTS, page 53-56. IEEE, (2008)A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1423-1434 (2020)Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (4): 346-350 (2016)A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications., , , , , and . IEEE J. Solid State Circuits, 43 (2): 321-329 (2008)ManiDec: Manifold Constrained Low-Rank and Sparse Decomposition., , , , , , and . IEEE Access, (2019)A multi-core mapping implementation of 3780-point FFT., , , , and . ISOCC, page 289-292. IEEE, (2012)