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Disambiguation of "Chiu, Yun"

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A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation.

, , , and . J. Sel. Topics Signal Processing, 3 (3): 374-383 (2009)

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Yü Chih Chiu

Chung-wai Chiu

Tiziana Chiusi

Wei-Hua Chiu

Alessandro Chiumento

 

Other publications of authors with the same name

CMOS RF transmitter with integrated power amplifier utilizing digital equalization., , , , and . CICC, page 403-406. IEEE, (2009)Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1306-1314 (2015)Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators., and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (4): 690-698 (2011)A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling., , , , and . IEEE J. Solid State Circuits, 45 (11): 2262-2272 (2010)A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR., , , and . IEEE J. Solid State Circuits, 51 (12): 2893-2905 (2016)A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs., and . ISCAS, page 1241-1244. IEEE, (2007)Background calibration of time-interleaved ADC using direct derivative information., and . ISCAS, page 2456-2459. IEEE, (2013)A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR., , and . IEEE J. Solid State Circuits, 39 (12): 2139-2151 (2004)A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration., , and . CICC, page 1-4. IEEE, (2012)A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer., , and . A-SSCC, page 1-4. IEEE, (2015)