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Disambiguation of "Verbauwhede, Ingrid"

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Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.

, and . ISVLSI, page 83-88. IEEE Computer Society, (2004)

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Ingrid Lühr

Internationale Rechnungslegung für kleine und mittelgroße Unternehmen. Uni Hagen, (2009)

Ingrid Meuche

Ingrid Kunzel

Ingrid Zeep

Ingrid Eisenmann

 

Other publications of authors with the same name

A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems., , , and . IEEE Trans. Computers, 57 (12): 1714-1719 (2008)Masking ring-LWE., , , , and . J. Cryptographic Engineering, 6 (2): 139-153 (2016)The Impact of Error Dependencies on Ring/Mod-LWE/LWR Based Schemes., , and . PQCrypto, volume 11505 of Lecture Notes in Computer Science, page 103-115. Springer, (2019)Partition vs. Comparison Side-Channel Distinguishers: An Empirical Evaluation of Statistical Tests for Univariate Side-Channel Attacks against Two Unprotected CMOS Devices., , and . ICISC, volume 5461 of Lecture Notes in Computer Science, page 253-267. Springer, (2008)Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip, , , , and . CoRR, (2007)An embedded platform for privacy-friendly road charging applications., , and . DATE, page 867-872. IEEE Computer Society, (2010)ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling., , , , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018 (3): 267-292 (2018)A 334 μW 0.158 mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom-Cook Multiplication., , , , , , and . IEEE J. Solid State Circuits, 58 (8): 2383-2398 (2023)Design and performance testing of a 2.29-GB/s Rijndael processor., , and . IEEE J. Solid State Circuits, 38 (3): 569-572 (2003)Towards efficient and automated side-channel evaluations at design time., , , , and . J. Cryptogr. Eng., 10 (4): 305-319 (2020)