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Disambiguation of "Rajski, Janusz"

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Low-Power Programmable PRPG With Test Compression Capabilities.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (6): 1063-1076 (2015)

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Janusz Gatniejewski

Janusz Panzer

Janusz Rat

Janusz Surzykiewicz

Janusz Bogdanowicz

 

Other publications of authors with the same name

On Linear Dependencies in Subspaces of LFSR-Generated Sequences., and . IEEE Trans. Computers, 45 (10): 1212-1216 (1996)Built-In Self-Test for Systems on Silicon., , and . VLSI Design, page 609-610. IEEE Computer Society, (1999)High Performance Dense Ring Generators., , , and . IEEE Trans. Computers, 55 (1): 83-87 (2006)Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)Self-test methodology for at-speed test of crosstalk in chip interconnects., , and . DAC, page 619-624. ACM, (2000)On necessary and nonconflicting assignments in algorithmic test pattern generation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (4): 515-530 (1994)High Volume Diagnosis in Memory BIST Based on Compressed Failure Data., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 441-453 (2010)Ring generators - new devices for embedded test applications., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (9): 1306-1320 (2004)Logic BIST With Capture-Per-Clock Hybrid Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)EDT Bandwidth Management in SoC Designs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1894-1907 (2012)