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Disambiguation of "Kobayashi, Haruo"

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Low-distortion signal generation for ADC testing.

, , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)

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Haruo Oba

Yoshitake Kobayashi

Wakiko Kobayashi

Wataru Kobayashi

Makoto Kobayashi

 

Other publications of authors with the same name

Estimation of circuit component values in buck converter using efficiency curve., , , and . ISPACS, page 895-900. IEEE, (2017)Flat passband gain design algorithm for 2nd-order RC polyphase filter., , , , , and . ASICON, page 1-4. IEEE, (2015)Single inductor DC-DC converter with bipolar outputs using charge pump., , , , , , , , , and 2 other author(s). APCCAS, page 460-463. IEEE, (2010)Asynchronous capacitive SAR ADC based on Hopfield network., , , , , and . IEICE Electron. Express, 19 (18): 20220276 (2022)Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption., , and . IEICE Electron. Express, 10 (11): 20130289 (2013)Image processing regularization filters on layered architecture., , , and . Neural Networks, 6 (3): 327-350 (1993)Spatial and temporal stability of vision chips including parasitic inductances and capacitances., and . ICASSP, page 1081-1084. IEEE, (1998)A Practical Analog BIST Cooperated with an LSI Tester., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (2): 465-468 (2006)Analysis of Coupled Inductors for Low-Ripple Fast-Response Buck Converter., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (2): 451-455 (2009)CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation., , , , and . IEEE J. Solid State Circuits, 47 (11): 2701-2710 (2012)