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Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (12): 2222-2230 (2018)Supplemental PDK for ASAP7 Using Synopsys Flow., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2021)Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 106 (3): 551-559 (March 2023)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5568-5581 (2022)A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery., , , , and . SOCC, page 1-6. IEEE, (2023)Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation., , and . SoCC, page 42-47. IEEE, (2014)Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2015)An impact of process variation on supply voltage dependence of logic path delay variation., , and . VLSI-DAT, page 1-4. IEEE, (2015)Process variation aware D-Flip-Flop design using regression analysis., and . ISQED, page 88-93. IEEE, (2018)Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction., , , and . SOCC, page 1-6. IEEE, (2023)